SH7261 Datasheet, PDF(858/1348 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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SH7261 Datasheet, PDF (858/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

Bit 6 â Halt during Bus Off (MCR6): MCR6 enables or disables entering Halt mode

immediately when MCR1 is set during Bus Off. This bit can be modified only in Reset or Halt

mode. Please note that when Halt is entered in Bus Off the CAN engine is also recovering

immediately to Error Active mode.

Bit6: MCR6

0

1

Description

Don't enter Halt mode during Bus Off but wait up to end of recovery

sequence (Initial value)

Enter Halt mode immediately during Bus Off if MCR[1] or MCR[14] are

asserted.

Bit 5 â Sleep Mode (MCR5): Enables or disables Sleep mode transition. If this bit is set, while

RCAN-ET is in halt mode, the transition to sleep mode is enabled. Setting MCR5 is allowed after

entering Halt mode. The two Error Counters (REC, TEC) will remain the same during Sleep

mode. This mode will be exited in two ways:

1. by writing a '0' to this bit position,

2. or, if MCR[7] is enabled, after detecting a dominant bit on the CAN bus.

If Auto wake up mode is disabled, RCAN-ET will ignore all CAN bus activities until the sleep

mode is terminated. When leaving this mode the RCAN-ET will synchronise to the CAN bus (by

checking for 11 recessive bits) before joining CAN Bus activity. This means that, when the No.2

method is used, RCAN-ET will miss the first message to receive. CAN transceivers stand-by

mode will also be unable to cope with the first message when exiting stand by mode, and the S/W

needs to be designed in this manner.

In sleep mode only the following registers can be accessed: MCR, GSR, IRR and IMR.

Important: RCAN-ET is required to be in Halt mode before requesting to enter in Sleep mode.

That allows the CPU to clear all pending interrupts before entering sleep mode. Once all interrupts

are cleared RCAN-ET must leave the Halt mode and enter Sleep mode simultaneously (by writing

MCR[5] = 1 and MCR[1] = 0 at the same time).

Bit 5: MCR5

0

1

Description

RCAN-ET sleep mode released (Initial value)

Transition to RCAN-ET sleep mode enabled

Bit 4 â Reserved. The written value should always be '0' and the returned value is '0'.

Rev. 2.00 Sep. 07, 2007 Page 826 of 1312

REJ09B0320-0200

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