SH7261 Datasheet, PDF (426/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
• TIORL_0, TIORL_3, TIORL_4
Bit: 7
6
5
4
3
2
1
0
IOD[3:0]
IOC[3:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7 to 4 IOD[3:0] 0000 R/W I/O Control D0 to D3
Specify the function of TGRD.
See the following tables.
TIORL_0: Table 12.13
TIORL_3: Table 12.17
TIORL_4: Table 12.19
3 to 0 IOC[3:0] 0000 R/W I/O Control C0 to C3
Specify the function of TGRC.
See the following tables.
TIORL_0: Table 12.21
TIORL_3: Table 12.25
TIORL_4: Table 12.27
• TIORU_5, TIORV_5, TIORW_5
Bit: 7 6
——
Initial value: 0 0
R/W: R R
5
4
3
2
1
0
—
IOC[4:0]
0
0
0
0
0
0
R R/W R/W R/W R/W R/W
Bit
Bit Name
7 to 5 
4 to 0 IOC[4:0]
Initial
Value
All 0
00000
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
I/O Control C0 to C4
Specify the function of TGRU_5, TGRV_5, and
TGRW_5.
For details, see table 12.28.
Rev. 2.00 Sep. 07, 2007 Page 394 of 1312
REJ09B0320-0200