SH7261 Datasheet, PDF (846/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.2.4 Memory Map
The diagram of the memory map is shown below.
H'000
H'002
H'004
H'006
H'008
H'00A
H'00C
Bit 15
Bit 0
Master Control Register (MCR)
General Status Register(GSR)
Bit timing Configuration Register 1 (BCR1)
Bit timing Configuration Register 0 (BCR0)
Interrupt Request Register (IRR)
Interrupt Mask Register (IMR)
Transmit Error Counter Receive Error Counter
(TEC)
(REC)
H'020
H'022
Transmit Pending Register (TXPR1)
Transmit Pending Register (TXPR0)
H'02A
Transmit Cancel Register (TXCR0)
H'032
Transmit Acknowledge Register (TXACK0)
H'03A
Abort Acknowledge Register (ABACK0)
H'042
Data Frame Receive Pending Register (RXPR0)
H'04A
Remote Frame Pending Register (RFPR0)
H'052
Mailbox Interrupt Mask Register (MBIMR0)
H'05A
Unread Message Status Register (UMSR0)
Bit 15
H'0A0
H'0A4
Bit 0
H'100
H'104
H'108
H'10A
H'10C
H'10E
H'110
Mailbox-0 Control 0
(STDID, EXTID, RTR, IDE)
LAFM
0
1
2
3
Mailbox 0 Data (8 bytes)
4
5
6
7
Mailbox-0 Control 1 (NMC, MBC, DLC)
H'120
H'140
H'160
Mailbox-1 Control/LAFM/Data etc.
Mailbox-2 Control/LAFM/Data etc.
Mailbox-3 Control/LAFM/Data etc.
H'2E0
Mailbox-15 Control/LAFM/Data etc.
Note: The locations not used (between H'000 and H'2F2) are reserved and cannot be accessed.
Addresses shown above are offset addrsses. As for actual addresses, see section 30, List of Registers.
Figure 19.2 RCAN-ET Memory Map
Rev. 2.00 Sep. 07, 2007 Page 814 of 1312
REJ09B0320-0200