SH7261 Datasheet, PDF (814/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
Bit
Bit Name
31 to 29 
Initial
Value
All 0
28
DMRQ
0
27
UIRQ
0
R/W Description
R
Reserved
The read value is not guaranteed. The write value
should always be 0.
R
DMA Request Status Flag
This status flag allows the CPU to recognize the value
of the DMA request pin on the SSI module.
• TRMD = 0 (Receive mode)
If DMRQ = 1, the SSIRDR has unread data.
If SSIRDR is read, DMRQ = 0 until there is new
unread data.
• TRMD = 1 (Transmit mode)
If DMRQ = 1, SSITDR requires data to be written to
continue the transmission to the audio serial bus.
Once data is written to SSITDR, DMRQ = 0 until it
requires further transmit data.
R/W*¹ Underflow Error Interrupt Status Flag
This status flag indicates that data was supplied at a
lower rate than was required.
In either case, this bit is set to 1 regardless of the value
of the UIEN bit and can be cleared by writing 0 to this
bit.
If UIRQ = 1 and UIEN = 1, an interrupt occurs.
• TRMD = 0 (Receive mode)
If UIRQ = 1, SSIRDR was read before there was
new unread data indicated by the DMRQ or DIRQ
bit. This can lead to the same received sample
being stored twice by the host leading to potential
corruption of multi-channel data.
• TRMD = 1 (Transmit mode)
If UIRQ = 1, SSITDR did not have data written to it
before it was required for transmission. This will
lead to the same sample being transmitted once
more and a potential corruption of multi-channel
data. This is more serious error than a receive
mode underflow as the output SSI data results in
error.
Note: When underflow error occurs, the current data in
the data buffer of this module is transmitted until
the next data is filled.
Rev. 2.00 Sep. 07, 2007 Page 782 of 1312
REJ09B0320-0200