SH7261 Datasheet, PDF (661/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 14 Watchdog Timer (WDT)
Bit
Bit Name
5
TME
4, 3

2 to 0 CKS[2:0]
Initial
Value R/W Description
0
R/W Timer Enable
Starts and stops timer operation. Clear this bit to 0
when using the WDT in software standby mode or
when changing the clock frequency.
0: Timer disabled
Count-up stops and WTCNT value is retained
1: Timer enabled
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
000
R/W Clock Select
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (Pφ). The overflow period that is
shown inside the parenthesis in the table is the value
when the peripheral clock (Pφ) is 25 MHz.
Bits 2 to 0
Clock Ratio Overflow Cycle
000:
1 × Pφ
10.2 µs
001:
1/64 × Pφ
655.4 µs
010:
1/128 × Pφ
1.3 ms
011:
1/256 × Pφ
2.6 ms
100:
1/512 × Pφ
5.2 ms
101:
1/1024 × Pφ 10.5 ms
110:
1/4096 × Pφ 41.9 ms
111:
1/16384 × Pφ 167.8 ms
Note: If bits CKS[2:0] are modified when the WDT is
running, the up-count may not be performed
correctly. Ensure that these bits are modified
only when the WDT is not running.
Rev. 2.00 Sep. 07, 2007 Page 629 of 1312
REJ09B0320-0200