SH7261 Datasheet, PDF (838/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
18.4.7 Serial Bit Clock Control
This function is used to control and select which clock is used for the serial bus interface.
If the serial clock direction is set to input (SCKD = 0), the SSI module is in clock slave mode and
the shift register uses the bit clock that was input to the SSISCK pin.
If the serial clock direction is set to output (SCKD = 1), the SSI module is in clock master mode,
and the shift register uses the bit clock that was input from the AUDIO_CLK pin or AUDIO_X1
and AUDIO_X2 pins, or the bit clock that is generated by dividing them. This input clock is then
divided by the ratio in the serial oversampling clock divide ratio (CKDV) in SSICR and used as
the bit clock in the shift register.
In either case the module pin, SSISCK, is the same as the bit clock.
18.5 Usage Notes
18.5.1 Limitations from Overflow during Receive DMA Operation
If an overflow occurs while the receive DMA is in operation, the module should be restarted. The
receive buffer in the SSI consists of 32-bit registers that share the L and R channels. Therefore,
data to be received at the L channel may sometimes be received at the R channel if an overflow
occurs, for example, under the following condition: the control register (SSICR) has a 32-bit
setting for both data word length (DWL2 to DWL0) and system word length (SWL2 to SWL).
If an overflow is confirmed with the overflow error interrupt or overflow error status flag (the
OIRQ bit in SSISR), write 0 to the EN bit in SSICR and DMEN bit to disable DMA in the SSI
module, thus stopping the operation. (In this case, the controller setting should also be stopped.)
After this, write 0 to the OIRQ bit to clear the overflow status, set DMA again and restart the
transfer.
Rev. 2.00 Sep. 07, 2007 Page 806 of 1312
REJ09B0320-0200