SH7261 Datasheet, PDF (65/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
(11) Absolute Address
When data is accessed by an absolute address, the absolute address value should be placed in the
memory table in advance. That value is transferred to the register by loading the immediate data
during the execution of the instruction, and the data is accessed in register indirect addressing
mode.
With the SH-2A, when data is referenced using an absolute address not exceeding 28 bits, it is also
possible to transfer immediate data located in the instruction code to a register and to reference the
data in register indirect addressing mode. However, when referencing data using an absolute
address of 21 to 28 bits, an OR instruction must be used after the data is transferred to a register.
Table 2.6 Absolute Address Accessing
Classification
Up to 20 bits
21 to 28 bits
29 bits or more
SH-2A CPU
Example of Other CPU
MOVI20 #H'12345,R1
MOV.B @H'12345,R0
MOV.B @R1,R0
MOVI20S
OR
MOV.B
#H'12345,R1
#H'67,R1
@R1,R0
MOV.B @H'1234567,R0
MOV.L @(disp,PC),R1
MOV.B @H'12345678,R0
MOV.B @R1,R0
..................
.DATA.L H'12345678
(12) 16-Bit/32-Bit Displacement
When data is accessed by 16-bit or 32-bit displacement, the displacement value should be placed
in the memory table in advance. That value is transferred to the register by loading the immediate
data during the execution of the instruction, and the data is accessed in the indexed indirect
register addressing mode.
Table 2.7 Displacement Accessing
Classification
SH-2A CPU
Example of Other CPU
16-bit displacement MOV.W
@(disp,PC),R0
MOV.W @(H'1234,R1),R2
MOV.W
@(R0,R1),R2
..................
.DATA.W H'1234
Rev. 2.00 Sep. 07, 2007 Page 33 of 1312
REJ09B0320-0200