SH7261 Datasheet, PDF (133/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 5 Exception Handling
5.2 Resets
5.2.1 Input/Output Pins
Table 5.5 shows the configuration of pins relating to the resets.
Table 5.5 Pin Configuration
Pin Name
Symbol I/O
Power-on reset RES
Input
Manual reset MRES Input
Function
When this pin is driven low, this LSI shifts to the power-on
reset processing
When this pin is driven low, this LSI shifts to the manual
reset processing.
5.2.2 Types of Reset
A reset is the highest-priority exception handling source. There are two kinds of resets, power-on
and manual. As shown in table 5.6, the CPU state is initialized by both a power-on reset and a
manual reset. The FPU state is initialized by a power-on reset, but not by a manual reset. On-chip
peripheral module registers except a few registers are initialized by a power-on reset, but not by a
manual reset.
Table 5.6 Reset States
Conditions for Transition to Reset State
Type
WDT
RES H-UDI Command MRES Overflow
Power-on Low —
—
—
reset
High H-UDI reset assert —
—
command is set
High Command other —
than H-UDI reset
assert is set
Power-on
reset
Internal States
CPU
Initialized
Initialized
On-Chip
Peripheral
Modules, I/O Port
Initialized^*1
Initialized^*1
WRCSR of
WDT, FRQCR
of CPG
Initialized
Initialized
Initialized Initialized^*1
Not initialized
Rev. 2.00 Sep. 07, 2007 Page 101 of 1312
REJ09B0320-0200