SH7261 Datasheet, PDF (807/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
18.3.1 Control Register (SSICR)
SSICR is a readable/writable 32-bit register that controls the IRQ, selects the polarity status, and
sets operating mode.
SSICR is initialized to H'00000000 by a power-on reset or in deep standby mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — DMEN UIEN OIEN IIEN DIEN CHNL[1:0]
DWL[2:0]
SWL[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL —
CKDV[2:0] MUEN — TRMD EN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 29 
All 0 R
Reserved
The read value is not guaranteed. The write value
should always be 0.
28
DMEN
0
R/W DMA Enable
Enables/disables the DMA request.
0: DMA request is disabled.
1: DMA request is enabled.
27
UIEN
0
R/W Underflow Interrupt Enable
0: Underflow interrupt is disabled.
1: Underflow Interrupt is enabled.
26
OIEN
0
R/W Overflow Interrupt Enable
0: Overflow interrupt is disabled.
1: Overflow interrupt is enabled.
25
IIEN
0
R/W Idle Mode Interrupt Enable
0: Idle mode interrupt is disabled.
1: Idle mode interrupt is enabled.
Rev. 2.00 Sep. 07, 2007 Page 775 of 1312
REJ09B0320-0200