SH7261 Datasheet, PDF (269/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
9.4.15 SDRAMm Mode Register (SDmMOD) (m = 0, 1)
SDmMOD specifies the values to be written to the SDRAM mode register or extended mode
register. Writing to this register causes a mode register set command or extended mode register set
command to be issued automatically to SDRAM.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15
—
Initial value: 0
R/W: R
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DMR[14:0]
———————————————
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W
31 to 15 
All 0
R
14 to 0 DMR[14:0] Undefined R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Mode Register Setting
Writing to these bits causes a mode register set
command or extended mode register set command to
be issued to SDRAM. The setting of the DMR bits is
output as A16 to A2 signals. The distinction between
the mode register set command and extended mode
register set command is made on the bases of the
SDRAM bank address.
Write operation: A mode register set command is
issued.
DMR bit
b14 b13
...
b0
↓↓
↓
A16 to A2 signal A16 A15
...
A2
Notes: The following points should be kept in mind regarding SDRAMm mode register settings.
1. Make sure to set a burst length of 1 for SDRAM. Operation cannot be guaranteed with
settings other than burst length 1.
2. The SDRAM column latency must match the setting of the SDRAM controller column
latency setting bits (DCL) in SDRAMC. Operation cannot be guaranteed if the latency
settings do not agree.
3. Check to make sure the status bits (DSRFST, DPWDST, DDPDST, and DMRSST) in
the SDRAM status register (SDSTR) are all cleared to 0.
Rev. 2.00 Sep. 07, 2007 Page 237 of 1312
REJ09B0320-0200