SH7261 Datasheet, PDF (1050/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 22 A/D Converter (ADC)
Bit
11 to 8
Bit Name
TRGS[3:0]
Initial
Value
0000
7, 6
CKS[1:0] 01
R/W Description
R/W Timer Trigger Select
These bits enable or disable starting of A/D conversion
by a trigger signal.
0000: Start of A/D conversion by external trigger input is
disabled
0001: A/D conversion is started by conversion trigger
TRGAN from MTU2
0010: A/D conversion is started by conversion trigger
TRG0N from MTU2
0011: A/D conversion is started by conversion trigger
TRG4AN from MTU2
0100: A/D conversion is started by conversion trigger
TRG4BN from MTU2
0101: Setting prohibited
0110: Setting prohibited
0111: Setting prohibited
1000: Setting prohibited
1001: A/D conversion is started by ADTRG
1010: A/D conversion is started by conversion trigger
from the TMR
1011 to 1111: Setting prohibited
R/W Clock Select
These bits select the A/D conversion time. *² Set the
A/D conversion time while A/D conversion is halted
(ADST = 0).
00: Conversion time = 138 states (maximum)
01: Conversion time = 274 states (maximum)
10: Conversion time = 546 states (maximum)
11: Setting prohibited
Rev. 2.00 Sep. 07, 2007 Page 1018 of 1312
REJ09B0320-0200