SH7261 Datasheet, PDF (287/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
(4) Self-Refresh
Transition to and from self-refresh mode is controlled by means of settings to SDRAM refresh
control register 0 (SDRFCNT0). Transition to and from self-refresh mode takes place
simultaneously for all channels.
An auto-refresh cycle operation takes place immediately before transition to self-refresh mode.
While in self-refresh mode the CKE signal is low level. Immediately after recovery from self-
refresh mode an auto-refresh cycle is triggered.
Figure 9.7 shows the timing of transition to self-refresh mode, and figure 9.8 shows the timing of
recovery from self-refresh mode.
Auto-refresh cycle
Self-refresh mode (CKE = L)
CKIO
SDRAM command
RFA DSL DSL RFS
DREFW
DSL: Deselect command
RFA: Auto-refresh command
RFS: Self-refresh entry command
Figure 9.7 Example of Timing of Transition to Self-Refresh Mode
(DREFW Bit Set Value: 0010)
CKIO
Self-refresh mode
(CKE = L)
Self-refresh clearing
interval
Auto-refresh
cycle
SDRAM command
REX DSL DSL
DSL: Deselect command
RFA: Auto-refresh command
RFX: Self-refresh exit command
DREFW
RFA DSL DSL
DREFW
Figure 9.8 Example of Timing of Recovery from Self-Refresh Mode
(DREFW Bit Set Value: 0010)
Rev. 2.00 Sep. 07, 2007 Page 255 of 1312
REJ09B0320-0200