SH7261 Datasheet, PDF (241/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
9.3 Area Overview
9.3.1 Address Map
In the architecture, this LSI has a 32-bit address space, which is divided into cache-enabled, cache-
disabled, and on-chip spaces (on-chip RAM, on-chip peripheral modules, and reserved areas)
according to the upper bits of the address.
External address spaces CS5 to CS0 are cache-enabled when internal address A29 = 0 and cache-
disabled when A29 = 1. The CS6 space is always cache-disabled.
The kind of memory to be connected and the data bus width are specified independently for each
partial space. The address map for the external address space is listed below.
Table 9.2 Address Map
Internal Address
H'00000000 to H'03FFFFFF
H'04000000 to H'07FFFFFF
H'08000000 to H'0BFFFFFF
H'0C000000 to H'0FFFFFFF
H'10000000 to H'13FFFFFF
H'14000000 to H'17FFFFFF
H'18000000 to H'1BFFFFFF
H'1C000000 to H'1FFFFFFF
H'20000000 to H'23FFFFFF
H'24000000 to H'27FFFFFF
H'28000000 to H'2BFFFFFF
H'2C000000 to H'2FFFFFFF
H'30000000 to H'33FFFFFF
H'34000000 to H'37FFFFFF
H'38000000 to H'3BFFFFFF
H'3C000000 to H'3FFFFFFF
Space
CS0
CS1
SDRAM0
SDRAM1
CS2
CS3
CS4
CS5
CS0
CS1
SDRAM0
SDRAM1
CS2
CS3
CS4
CS5
Memory to be Connected
Normal space
Normal space
SDRAM
SDRAM
Normal space
Normal space
Normal space
Normal space
Normal space
Normal space
SDRAM
SDRAM
Normal space
Normal space
Normal space
Normal space
Cache
Cache-
enabled
Cache-
disabled
Rev. 2.00 Sep. 07, 2007 Page 209 of 1312
REJ09B0320-0200