SH7261 Datasheet, PDF (305/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Multiple read
CKIO
SDRAM command
ACT DSL RD
RD
RD
RD PRA DSL
Data bus
d0
d1
d2
d3
DRCD
(ACR-RD)
DCL
(RD-d)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
RD: Read command
PRA: Precharge-all command
DPCG
(PRA-next)
Figure 9.31 Multiple Read Timing Example 2
Multiple read
CKIO
SDRAM command
ACT DSL RD
RD
RD
RD
PRA DSL DSL
Data bus
d0
d1
d2
d3
DRCD
(ACT-RD)
DRAS
(ACT-PRA)
DCL
(RD-d)
DPCG
(PRA-next)
ACT: Row and bank activation command
RD: Read command
PRA: Precharge-all command
Figure 9.32 Multiple Read Timing Example 3
Rev. 2.00 Sep. 07, 2007 Page 273 of 1312
REJ09B0320-0200