SH7261 Datasheet, PDF (1173/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
9
MRESF
0
R/(W)* MRES Flag
0: No interrupt on MRES pin
1: Interrupt on MRES pin
8
NMIF
0
R/(W)* NMI Flag
0: No interrupt on NMI pin
1: Interrupt on NMI pin
7
IRQ7F
0
R/(W)* IRQ7 Flag
0: No interrupt on IRQ7 pin
1: Interrupt on IRQ7 pin
6
IRQ6F
0
R/(W)* IRQ6 Flag
0: No interrupt on IRQ6 pin
1: Interrupt on IRQ6 pin
5
IRQ5F
0
R/(W)* IRQ5 Flag
0: No interrupt on IRQ5 pin
1: Interrupt on IRQ5 pin
4
IRQ4F
0
R/(W)* IRQ4 Flag
0: No interrupt on IRQ4 pin
1: Interrupt on IRQ4 pin
3
IRQ3F
0
R/(W)* IRQ3 Flag
0: No interrupt on IRQ3 pin
1: Interrupt on IRQ3 pin
2
IRQ2F
0
R/(W)* IRQ2 Flag
0: No interrupt on IRQ2 pin
1: Interrupt on IRQ2 pin
1
IRQ1F
0
R/(W)* IRQ1 Flag
0: No interrupt on IRQ1 pin
1: Interrupt on IRQ1 pin
0
IRQ0F
0
R/(W)* IRQ0 Flag
0: No interrupt on IRQ0 pin
1: Interrupt on IRQ0 pin
Note: * Only 0 can be written after reading 1 to clear the flag.
Even when IRQ is input after a manual reset has been accepted as a source canceling
deep standby, the IRQ flag is not set.
Rev. 2.00 Sep. 07, 2007 Page 1141 of 1312
REJ09B0320-0200