SH7261 Datasheet, PDF (398/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.9 Units of Transfer and Positioning of Bytes for Transfer
The number of bits (transfer data size) for a single data transfer can be selected from among the
byte (8 bits), word (16 bits), and the longword (32 bits).
Figure 11.12 is an example of DMA data-byte control for a 32-bit wide bus.
This transfer data size cannot exceed either of the data bus bit widths supported by the source and
destination for DMA transfer. The data bus widths are fixed by the hardware.
8-bit transfer
State of
address bits
Source side
H'FF00 4000
H'FF00 4001
H'FF00 4002
H'FF00 4003
DMAC internal 32-bit data buffers
D0 to D31
D0 toD31
Destination side
H'0040 0203
H'0040 0204
H'0040 0205
H'0040 0206
State of
address bits
16-bit transfer
State of
address bits
Source side
H'FF00 8002
H'FF00 8004
DMAC internal 32-bit data buffers
D0 to D31
D0 to D31
Destination side
H'FF60 0806
H'FF60 0808
State of
address bits
: Byte/bytes being handled
Figure 11.12 Example of DMA Data-Byte Control for 32-bit Bus Width
Rev. 2.00 Sep. 07, 2007 Page 366 of 1312
REJ09B0320-0200