SH7261 Datasheet, PDF (93/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
Instruction
Instruction Code
Operation
Execution
Cycles
T Bit
FMOV.S @Rm, FRn
1111nnnnmmmm1000 (Rm) →FRn
1

FMOV.D @Rm, DRn
1111nnn0mmmm1000 (Rm) →DRn
2

FMOV.S @(disp12,Rm),FRn 0011nnnnmmmm0001 (disp×4+Rm) →FRn
1

0111dddddddddddd
FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001 (disp×8+Rm) →DRn
2

0111dddddddddddd
FMOV.S FRm, @(R0,Rn)
1111nnnnmmmm0111 FRm→ (R0+Rn)
1

FMOV.D DRm, @( R0,Rn ) 1111nnnnmmm00111 DRm→ (R0+Rn)
2

FMOV.S FRm, @-Rn
1111nnnnmmmm1011 Rn-=4, FRm→(Rn)
1

FMOV.D DRm, @-Rn
1111nnnnmmm01011 Rn-=8, DRm→(Rn)
2

FMOV.S FRm, @Rn
1111nnnnmmmm1010 FRm→(Rn)
1

FMOV.D DRm, @Rn
1111nnnnmmm01010 DRm→(Rn)
2

FMOV.S FRm, @(disp12,Rn) 0011nnnnmmmm000100 FRm→(disp×4+Rn)
1

11dddddddddddd
FMOV.D DRm, @(disp12,Rn) 0011nnnnmmm0000100 DRm→(disp×8+Rn)
2

11dddddddddddd
FMUL FRm, FRn
1111nnnnmmmm0010 FRn×FRm→FRn
1

FMUL DRm, DRn
1111nnn0mmm00010 DRn×DRm→DRn
6

FNEG FRn
1111nnnn01001101 -FRn→FRn
1

FNEG DRn
1111nnn001001101 -DRn→DRn
1

FSCHG
1111001111111101 FPSCR.SZ=~FPSCR.SZ 1

FSQRT FRn
1111nnnn01101101 √FRn→FRn
9

FSQRT DRn
1111nnn001101101 √DRn→DRn
22

FSTS FPUL,FRn
1111nnnn00001101 FPUL→FRn
1

FSUB FRm, FRn
1111nnnnmmmm0001 FRn-FRm→FRn
1

FSUB DRm, DRn
1111nnn0mmm00001 DRn-DRm→DRn
6

FTRC FRm, FPUL
1111mmmm00111101 (long)FRm→FPUL
1

FTRC DRm, FPUL
1111mmm000111101 (long)DRm→FPUL
2

Compatibility
SH2E SH4
SH-2A/
SH2A-FPU
Yes Yes Yes
Yes Yes
Yes
Yes
Yes Yes Yes
Yes Yes
Yes Yes Yes
Yes Yes
Yes Yes Yes
Yes Yes
Yes
Yes
Yes Yes Yes
Yes Yes
Yes Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes
Yes Yes Yes
Yes Yes
Rev. 2.00 Sep. 07, 2007 Page 61 of 1312
REJ09B0320-0200