SH7261 Datasheet, PDF (1339/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Instruction features ................................... 30
Instruction format ..................................... 38
Instruction set ........................................... 42
Integer division instructions ................... 113
Interrupt controller (INTC)..................... 119
Interrupt exception handling................... 110
Interrupt exception handling vectors
and priorities ........................................... 141
Interrupt priority level............................. 109
Interrupt response time ........................... 153
IRQ interrupts ......................................... 138
J
Jump table base register (TBR) ................ 26
L
List of registers ..................................... 1167
Load-store architecture ............................. 31
Local acceptance filter mask (LAFM).... 821
Logic operation instructions ..................... 55
LRU ........................................................ 189
M
Mailbox................................................... 812
Mailbox control ...................................... 813
Mailbox structure.................................... 816
Manual reset ........................................... 104
Master receive operation......................... 751
Master transmit operation ....................... 749
Measurement circuit ............................. 1289
Memory-mapped cache .......................... 200
Message control field.............................. 817
Message data fields................................. 822
Message receive sequence ...................... 865
Message transmission sequence.............. 863
Micro processor interface (MPI)............. 812
Module standby function ...................... 1151
MTU2 functions...................................... 374
MTU2 interrupts ..................................... 537
MTU2 module timing ........................... 1277
MTU2 output pin initialization ............... 568
Multi mode............................................ 1023
Multi-function timer pulse unit 2
(MTU2)................................................... 373
Multiplexed pin table (Port A) .............. 1061
Multiplexed pin table (Port B) .............. 1063
Multiplexed pin table (Port C) .............. 1065
Multiplexed pin table (Port D) .............. 1067
Multiplexed pin table (Port E) .............. 1068
Multiplexed pin table (Port F)............... 1068
Multiply and accumulate register
high (MACH)............................................ 26
Multiply and accumulate register low
(MACL) .................................................... 26
Multiply/Multiply-and-accumulate
operations.................................................. 31
N
NaN........................................................... 70
NMI interrupt.......................................... 137
Noise filter .............................................. 761
Nonlinearity error.................................. 1032
Non-numbers (NaN) ................................. 69
Note on making a transition to deep
standby mode ........................................ 1150
Note on using a PLL oscillation circuit..... 94
Note on using crystal resonator................. 93
O
Offset error............................................ 1032
On-chip peripheral module interrupts ........... 139
On-chip RAM ....................................... 1123
Operation in asynchronous mode............ 708
Operation in clocked synchronous
mode ....................................................... 717
Rev. 2.00 Sep. 07, 2007 Page 1307 of 1312
REJ09B0320-0200