SH7261 Datasheet, PDF (583/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(4) Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figures 12.105 and
12.106 show the timing for status flag clearing by the CPU, and figure 12.107 show the timing for
status flag clearing by the DMAC.
TSR write cycle
T1
T2
Pφ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 12.105 Timing for Status Flag Clearing by CPU (Channels 0 to 4)
TSR write cycle
T1
T2
Pφ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 12.106 Timing for Status Flag Clearing by CPU (Channel 5)
Rev. 2.00 Sep. 07, 2007 Page 551 of 1312
REJ09B0320-0200