SH7261 Datasheet, PDF (1337/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Index
Numerics
16-bit counter mode................................ 618
16-bit/32-bit displacement ........................ 33
8-bit timers (TMR) ................................. 601
A
A/D conversion time (multi mode and
scan mode)............................................ 1030
A/D conversion time (single mode)...... 1029
A/D conversion timing ......................... 1029
A/D converter (ADC) ........................... 1011
A/D converter activation......................... 539
A/D converter characteristics................ 1290
A/D converter start request delaying
function................................................... 529
A/D trigger input timing ....................... 1285
Absolute address....................................... 33
Absolute address accessing....................... 33
Absolute maximum ratings................... 1249
AC characteristics................................. 1258
AC characteristics measurement
conditions ............................................. 1289
Address array.................................. 188, 200
Address array read .................................. 200
Address errors......................................... 105
Address map ........................................... 209
Address-array write
(associative operation) ............................ 201
Address-array write (non-associative
operation)................................................ 201
Addressing modes..................................... 34
Advanced user debugger II
(AUD-II)............................................... 1161
Analog input pin ratings ....................... 1035
Arithmetic operation instructions ............. 52
B
Bit manipulation instructions .................... 63
Bit synchronous circuit ........................... 767
Block diagram........................................... 11
Branch instructions ................................... 57
Break detection and processing............... 727
Break on data access cycle...................... 179
Break on instruction fetch cycle.............. 178
Bus monitor............................................. 291
Bus state controller (BSC) ...................... 205
Bus timing............................................. 1264
C
Cache ...................................................... 187
Calculating exception handling vector
table addresses ........................................ 100
CAN interface ......................................... 813
CAN sleep mode ..................................... 859
Canceling software standby mode .......... 633
Cascaded connection............................... 618
CD-ROM decoder (ROM-DEC) ............. 943
Changing the division ratio ....................... 92
Changing the frequency .................... 91, 633
Changing the multiplication rate............... 91
Clock frequency control circuit................. 79
Clock operating modes ............................. 81
Clock pulse generator (CPG) .................... 77
Clock timing ......................................... 1258
Clocked synchronous serial format......... 757
Coherency of cache and external
memory ................................................... 200
Compare match count mode ................... 619
Compare match signal............................. 616
Complementary PWM mode .................. 493
Control signal timing ............................ 1262
Controller area network (RCAN-ET)...... 809
Rev. 2.00 Sep. 07, 2007 Page 1305 of 1312
REJ09B0320-0200