SH7261 Datasheet, PDF (85/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Instruction
CLIPS.B Rn
CLIPS.W Rn
CLIPU.B Rn
CLIPU.W Rn
DIV1
Rm,Rn
DIV0S Rm,Rn
DIV0U
DIVS
R0,Rn
DIVU
R0,Rn
DMULS.L Rm,Rn
DMULU.L Rm,Rn
DT
Rn
EXTS.B Rm,Rn
EXTS.W Rm,Rn
EXTU.B Rm,Rn
Section 2 CPU
Instruction Code
0100nnnn10010001
0100nnnn10010101
0100nnnn10000001
0100nnnn10000101
0011nnnnmmmm0100
0010nnnnmmmm0111
0000000000011001
0100nnnn10010100
0100nnnn10000100
0011nnnnmmmm1101
0011nnnnmmmm0101
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
Operation
Execu-
tion
Cycles
T Bit
Compatibility
SH2,
SH2E SH4 SH-2A
When Rn > (H'0000007F), 1

Yes
(H'0000007F) → Rn, 1 → CS
when Rn < (H'FFFFFF80),
(H'FFFFFF80) → Rn, 1 → CS
When Rn > (H'00007FFF), 1

Yes
(H'00007FFF) → Rn, 1 → CS
When Rn < (H'FFFF8000),
(H'FFFF8000) → Rn, 1 → CS
When Rn > (H'000000FF), 1

Yes
(H'000000FF) → Rn, 1 → CS
When Rn > (H'0000FFFF), 1

Yes
(H'0000FFFF) → Rn, 1 → CS
1-step division (Rn ÷ Rm)
1
Calcu- Yes
lation
result
Yes Yes
MSB of Rn → Q,
1
MSB of Rm → M, M ^ Q → T
Calcu- Yes
lation
result
Yes Yes
0 → M/Q/T
1
0
Yes Yes Yes
Signed operation of Rn ÷ R0 36

Yes
→ Rn 32 ÷ 32 → 32 bits
Unsigned operation of Rn ÷ R0 34

Yes
→ Rn 32 ÷ 32 → 32 bits
Signed operation of Rn × Rm 2
→ MACH, MACL
32 × 32 → 64 bits

Yes Yes Yes
Unsigned operation of Rn × 2
Rm → MACH, MACL
32 × 32 → 64 bits

Yes Yes Yes
Rn – 1 → Rn
1
When Rn is 0, 1 → T
When Rn is not 0, 0 → T
Com- Yes
parison
result
Yes Yes
Byte in Rm is
sign-extended → Rn
1

Yes Yes Yes
Word in Rm is
sign-extended → Rn
1

Yes Yes Yes
Byte in Rm is
zero-extended → Rn
1

Yes Yes Yes
Rev. 2.00 Sep. 07, 2007 Page 53 of 1312
REJ09B0320-0200