SH7261 Datasheet, PDF (391/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.7 DMA Requests
11.7.1 Sources of DMA Requests
The 38 sources of DMA requests include the software trigger and various DMA request signal
inputs.
The DMA request source for each channel is specified by the DMA request source select bits
(DTCG) in the corresponding DMA control register A (DMCNTAn).
11.7.2 Synchronous Circuits for DMA Request Signals
For each channel of the DMAC, a synchronous circuit is incorporated to manage DMA requests,
which are asynchronously input. As a result, a blank period of a few clock cycles appears between
activation of the DMA request and actual reflection of the request in the DMA request bits
(DREQ) of DMA control register B (DMCNTBn). Figure 11.6 shows an example of timing
between the input of a DMA request and the DMA request bit.
Edge sense setting (falling edge sense)
System clock
DMA request input
DMA request bit
DMA request bit is on input
of the valid edge
Level sense setting (low level sense)
System clock
DMA request bit is maintained regardless
of changes in the level of the DMA request input
DMA request input
DMA request bit
DMA request bit is set when
the active level has been sampled
[Legend]
at the end of two clock periods.
: Sampling point for DMA request
DMA request bit is cleared
one cycle after sampling of
the inactive level.
Figure 11.6 Example of Timing between DMA Request Input and DMA Request Bit
Rev. 2.00 Sep. 07, 2007 Page 359 of 1312
REJ09B0320-0200