SH7261 Datasheet, PDF (869/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.4.4 Interrupt Request Register (IRR)
The interrupt register (IRR) is a 16-bit read/write-clearable register containing status flags for the
various interrupt sources.
• IRR (Address = H'008)
Bit: 15
—
Initial value: 0
R/W: R
14 13 12 11
— IRR13 IRR12 —
0
0
0
0
R R/W R/W R
10 9
8
7
6
5
4
3
2
1
0
— IRR9 IRR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0
0
0
0
0
0
0
0
0
0
0
1
R R R R/W R/W R/W R/W R/W R R R/W
Bits 15 to 14: Reserved.
Bit 13 - Message Error Interrupt (IRR13): This interrupt indicates that:
• A message error has occurred when in test mode.
• Note: If a Message Overload condition occurs when in Test Mode, then this bit will not be set.
When not in test mode this interrupt is inactive.
Bit 13: IRR13
0
1
Description
message error has not occurred in test mode (Initial value)
[Clearing condition] Writing 1
[Setting condition] message error has occurred in test mode
Rev. 2.00 Sep. 07, 2007 Page 837 of 1312
REJ09B0320-0200