SH7261 Datasheet, PDF (296/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
(c) Byte Access Control by DQM
Figures 9.21 and 9.22 show timing examples for byte accesses to the SDRAM with a 16-bit bus
width. In the SDRAM access, the DQM signal is asserted when data is masked.
CKIO
SDRAM command
DQM1
DQM0
Data bus [15:8]
Data bus [7:0]
ACT WR PRA
Low level
High-Z
d0
Figure 9.21 Byte Write Timing to SDRAM with 16-Bit Bus Width (Example)
CKIO
SDRAM command
DQM1
DQM0
Data bus [15:8]
Data bus [7:0]
ACT RD DSL PRA
Low level
d0
High-Z
Figure 9.22 Byte Read Timing from SDRAM with 16-Bit Bus Width (Example)
Rev. 2.00 Sep. 07, 2007 Page 264 of 1312
REJ09B0320-0200