SH7261 Datasheet, PDF (253/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
9.4.5 CSn Wait Control Register 1 (CS1WCNTn) (n = 0 to 6)
CS1WCNTn specifies the number of wait states inserted into the read/write cycle or page
read/page write cycle.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
———
CSRWAIT[4:0]
———
CSWWAIT[4:0]
Initial value: 0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
R/W: R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — CSPRWAIT[2:0] — — — — — CSPWWAIT[2:0]
Initial value: 0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
R/W: R R R R R R/W R/W R/W R R R R R R/W R/W R/W
Bit
Bit Name
31 to 29 
Initial
Value
All 0
28 to 24 CSRWAIT 11111
[4:0]
23 to 21 
All 0
20 to 16 CSWWAIT 11111
[4:0]
15 to 11 
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Read Cycle Wait Select
These bits specify the number of wait states inserted
into the initial normal read cycle and page read cycle.
00000: 0 wait states
:
11111: 31 wait states
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Write Cycle Wait Select
These bits specify the number of wait states inserted
into the initial normal write cycle and page write cycle.
00000: 0 wait states
:
11111: 31 wait states
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 221 of 1312
REJ09B0320-0200