SH7261 Datasheet, PDF (1006/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.29 Post-ECC Correction Header: Minutes Data Register (HEAD20)
HEAD20 indicates the minutes value in the header after ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD20[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit
7 to 0
Bit Name
HEAD20[7:0]
Initial
Value
All 0
R/W Description
R
Minutes value in the header after ECC correction
When MSF_LBA_SEL = 1, this register indicates the
first byte of the total number of sectors calculated from
M, S, and F.
21.3.30 Post-ECC Correction Header: Seconds Data Register (HEAD21)
HEAD21 indicates the seconds value in the header after ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD21[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit
7 to 0
Bit Name
HEAD21[7:0]
Initial
Value
All 0
R/W Description
R
Seconds value in the header after ECC correction
When MSF_LBA_SEL = 1, this register indicates the
second byte of the total number of sectors calculated
from M, S, and F.
Rev. 2.00 Sep. 07, 2007 Page 974 of 1312
REJ09B0320-0200