SH7261 Datasheet, PDF (584/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Pφ, Bφ
Address
Status flag
DMAC read cycle DMAC write cycyle
Source addess
Destination addres
Interrupt
request signal
Flag clear
signal
Figure 12.107 Timing for Status Flag Clearing by DMAC Activation (Channels 0 to 4)
12.7 Usage Notes
12.7.1 Module Standby Mode Setting
MTU2 operation can be disabled or enabled using the standby control register. The initial setting
is for MTU2 operation to be halted. Register access is enabled by clearing module standby mode.
For details, refer to section 27, Power-Down Modes.
12.7.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The MTU2 will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 12.108 shows the input clock
conditions in phase counting mode.
Rev. 2.00 Sep. 07, 2007 Page 552 of 1312
REJ09B0320-0200