SH7261 Datasheet, PDF (941/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
20.3.14 IEBus Lock Address Register 2 (IELA2)
IELA2 specifies the upper four bits of a locked address when a unit is locked.
IELA2 is initialized by a power-on reset or in deep standby.
Bit: 7
6
5
4
3
2
1
0
————
ILAU4
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Initial
Bit
Bit Name Value R/W Description
7 to 4 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
3 to 0 ILAU4
0000 R
Upper Four Bits of IEBus Locked Address
Stores the upper four bits of the master unit address
when a unit is locked. These bits are valid only when
the LCK bit in IEFLG is set
Rev. 2.00 Sep. 07, 2007 Page 909 of 1312
REJ09B0320-0200