SH7261 Datasheet, PDF (1331/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions and Additions in this Edition
Main Revisions and Additions in this Edition
Item
Table 1.2 Product Lineup
Page Revision (See Manual for Details)
10 Modified
Abbreviation
Product Code
R5S72611
R5S72611RB120FP
R5S72611RP100FP
R5S72611RP80FP
R5S72612
R5S72612RB120FP
R5S72612RP100FP
R5S72612RP80FP
R5S72613
R5S72613RB120FP
R5S72613RP100FP
R5S72613RP80FP
4.4.2 CKIO Control Register
(CKIOCR)
9.5.2 SDRAM Interface
(9) Read/Write Access
(c) Byte Access Control by DQM
Figure 9.26 SDRAMC Setting
Procedure
9.6.2 Write Buffer
9.6.3 Note on Transition to
Software Standby Mode or Deep
Standby Mode
90
264
268
288,
289
Modified
When this LSI is started in clock operating mode 3, CKIOCR is
initialized to H'00 by a power-on reset caused by the RES pin
or in deep standby mode. When this LSI is started in clock
operating mode 0 or 2, CKIOCR is initialized to H'01 by a
power-on reset caused by the RES pin or in deep standby
mode. This register is not initialized by an internal reset
triggered by an overflow of the WDT, a manual reset, in sleep
mode, or in software standby mode.
Added
Figure modified
Added
Rev. 2.00 Sep. 07, 2007 Page 1299 of 1312
REJ09B0320-0200