SH7261 Datasheet, PDF (266/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
9.4.13 SDRAMm Address Register (SDmADR) (m = 0, 1)
SDmADR specifies the data bus width and the channel size of SDRAM.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — DDBW[1:0] — — — — —
DSZ[2:0]
Initial value: 0
0
0
0
0
0 —— 0
0
0
0
0 ———
R/W: R R R R R R R/W R/W R R R R R R/W R/W R/W
Initial
Bit
Bit Name Value
R/W
31 to 10 
All 0
R
9, 8
DDBW[1:0] Undefined R/W
7 to 3 
All 0
R
2 to 0 DSZ[2:0] Undefined R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SDRAM Data Bit Width Setting
These bits specify the width of the SDRAM bus.
00: 8 bits
01: 16 bits
10: 32 bits
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Channel Size Setting
These bits specify the size of channels 0 and 1. If a
size smaller than SDRAM area 0 or 1 is selected, ghost
memory will result. When accessing 32-bit data in
SDRAM with a 16-bit bus width, the 16 bits of the first
half of the address (A1 = 0) are accessed first, and
then the 16 bits of the second half of the address (A1 =
1) are accessed.
Rev. 2.00 Sep. 07, 2007 Page 234 of 1312
REJ09B0320-0200