SH7261 Datasheet, PDF (1000/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.16 Buffer Overflow Status Register (CBUFST2)
CBUFST2 indicates that a sector-to-sector transition occurred before data transfer to the buffer is
completed.
Bit: 7
6
5
4
3
2
1
0
BUF_
NG
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit Bit Name
7
BUF_NG
6 to 0 
Initial
Value
0
All 0
R/W Description
R
Indicates that a sector-to-sector transition has occurred
before the data transfer to the buffer is completed. This
bit is set to 1 when the data of a third sector are input
while data for the output stream from the CD-ROM
decoder remains unread. No interrupt is generated.
Once this bit has been set, its value will not recover
unless it is reset by the LOGICRST bit in the
ROMDECRST register.
R
Reserved
These bits are always read as 0 and cannot be
modified.
21.3.17 Pre-ECC Correction Header: Minutes Data Register (HEAD00)
HEAD00 indicates the minutes value in the header before ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD00[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit
7 to 0
Bit Name
HEAD00[7:0]
Initial
Value
All 0
R/W Description
R
Minutes value in the header before ECC correction
Rev. 2.00 Sep. 07, 2007 Page 968 of 1312
REJ09B0320-0200