SH7261 Datasheet, PDF (989/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.5 Automatic Decoding Stop Control Register (CROMCTL3)
CROMCTL3 is used to select abnormal conditions on which decoding will be automatically
stopped. When decoding is stopped in response to any of the selected conditions, an IBUF
interrupt is generated and the condition is indicated in the CBUFST1 register. The setting of this
register becomes valid at the sector-to-sector transition
Bit: 7
STP_
ECC
Initial value: 0
R/W: R/W
6
STP_
EDC
0
R/W
5
—
0
R/W
43
STP_ STP_
MD MIN
00
R/W R/W
2
—
0
R/W
1
—
0
R/W
0
—
0
R/W
Initial
Bit Bit Name Value
R/W Description
7
STP_ECC 0
R/W When this bit is set to 1, decoding is stopped if an error
is found to be not correctable by ECC correction.
6
STP_EDC 0
R/W When this bit is set to 1, decoding is stopped if post-
correction EDC checking indicates an error.
5

0
R/W Reserved
This bit is always read as 0. The write value should
always be 0.
4
STP_MD 0
R/W When this bit is set to 1, decoding is stopped if the
sector has a mode or form setting that does not match
those of the immediately preceding sector.
3
STP_MIN 0
R/W When this bit is set to 1, decoding is stopped if a non-
sequential minutes, seconds, or frames (1/75 second)
value is encountered.
2 to 0 
All 0
R/W Reserved
These bits are always read as 0. The write value should
always be 0.
Note: The setting of this register is reapplied on each sector-to-sector transition.
Rev. 2.00 Sep. 07, 2007 Page 957 of 1312
REJ09B0320-0200