SH7261 Datasheet, PDF (1329/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Appendix
Pin Function
Pin State
Reset State
Power-On*²
Power-Down State
Type
Pin Name
Area 0 Data Bus Width
8 Bits 16 Bits 32 Bits ^Manual
Sleep
Software Deep
Standby Standby
I/O ports PC25 to PC22
I
I
I
I
I
Z
Z
PC21 to PC13
I
I
I
I/O
I/O
K
K
PC12, PC11
I
I
H
I/O
I/O
K
K
PC10
I
H
H
I/O
I/O
K
K
PC9
H
H
H
I/O
I/O
K
K
PC8
H
H
H
I/O
I/O
K
K
PC7 to PC1
I
I
I
I/O
I/O
K
K
PC0
H
H
H
I/O
I/O
K
K
PD16, PD15
I
I
I
I
I
Z
Z
PD14 to PD0
I
I
I
I/O
I/O
K
K
PE7 to PE0
I
I
I
I
I
Z
Z
PF7 to PF0
I
I
I
I/O
I/O
K
K
[Legend]
I: Input
O: Output
H: High-level output
L: Low-level output
Z: High-impedance
K: Input pins become high-impedance, and output pins retain their state.
Notes: 1. When pins for the connection with a crystal resonator are not used, the EXTAL and
AUDIO_X1 pins must be pulled up and the XTAL and AUDIO_X2 pins must be open.
The RTC_X1 pin must be connected to GND and the RTC_X2 must be open.
2. Power-on reset by low-level input to the RES pin. The pin states after a power-on reset
by the H-UDI reset assert command or WDT overflow are the same as the initial pin
states at normal operation (see section 25, Pin Function Controller (PFC)).
3. IRQ pins that can release deep standby mode are limited to PE7 to PE4 and PC25 to
PC22.
4. Z when the TAP controller of the H-UDI is neither the Shift-DR nor Shift-IR state.
5. L when the CKIO output is specified and Z when the CKIO output is stopped with the
setting of CKIOCR.
Rev. 2.00 Sep. 07, 2007 Page 1297 of 1312
REJ09B0320-0200