SH7261 Datasheet, PDF (351/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Bit
Bit Name
27 to 24 OPSEL
[3:0]
Initial
Value
R/W
Undefined R/W
Description
Number of Data Transfers in Single Operand Transfer
Selection
These bits are used to specify the number of single
data transfers in single operand transfer. The amount
of data specified by this bit is transferred continuously.
Channel arbitration is not executed until this amount of
data has been transferred (single operand transfer).
These bits are invalid when non-stop transfer (DSEL =
"11") is specified in the DMA transfer condition
selection bits (DSEL) of DMA control register A
(DMCNTAn).
Note:
Set the DMA current byte count register
(DMCBCTn) so that DMCBCTn becomes
H'000 0000 on transfer of the last data of the
operand transfer.
• When the transfer size is set to 8 bits
(SZSEL = "000"): Integer multiple of the
number of data transferred in each single
operand transfer (× 1, × 2, × 3, and so on)
• When the transfer size is set to 16 bits
(SZSEL = "001"): one operand transfer
data number multiplied by two (× 2, × 4, ×
6, and so on)
• When the transfer size is set to 32 bits
(SZSEL = "010"): one operand transfer
data number multiplied by four (× 4, × 8, ×
12, and so on)
Operation is not guaranteed when values other than
the above are set. For details, see section 11.3.3,
DMA Current Byte Count Register (DMCBCT) and
section 11.3.6, DMA Reload Byte Count Register
(DMRBCT).)
0000: 1 datum
0001: 2 data
0010: 4 data
0011: 8 data
0100: 16 data
0101: 32 data
0110: 64 data
0111: 128 data
1000 to 1111: Setting prohibited
Rev. 2.00 Sep. 07, 2007 Page 319 of 1312
REJ09B0320-0200