SH7261 Datasheet, PDF (1021/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.50 Interrupt Source Mask Control Register (INHINT)
INHINT controls masking of various interrupt requests in the CD-ROM decoder.
Bit: 7 6 5
INH INH INH
ISEC ITARG ISY
Initial value: 0 0 0
R/W: R/W R/W R/W
4
INH
IERR
0
R/W
3
2
1
0
INH INH PREINH PREINH
IBUF IREADY REQDM IREADY
0
0
0
0
R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W Description
7
INHISEC
0
R/W ISEC Interrupt Mask
When set to 1, masks the generation of ISEC interrupts
6
INHITARG 0
R/W ITARG Interrupt Mask
When set to 1, masks the generation of ITARG
interrupts
5
INHISY
0
R/W ISY Interrupt Mask
When set to 1, masks the generation of ISY interrupts
4
INHIERR
0
R/W IERR Interrupt Mask
When set to 1, masks the generation of IERR interrupts
3
INHIBUF
0
R/W IBUF Interrupt Mask
When set to 1, masks the generation of IBUF interrupts
2
INHIREADY 0
R/W IREADY Interrupt Mask
When set to 1, masks the generation of IREADY
interrupts
1
PREINH
0
REQDM
R/W Masks setting of the DMA transfer request interrupt flag
for the output data stream.
When set to 1, the DMA transfer request interrupt
source is not retained.
0
PREINH
0
IREADY
R/W Masks setting of the IREADY interrupt flag.
When set to 1, the interrupt source is not retained in the
IREADY flag.
Rev. 2.00 Sep. 07, 2007 Page 989 of 1312
REJ09B0320-0200