SH7261 Datasheet, PDF (1016/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.46 CD-ROM Decoder Reset Control Register (ROMDECRST)
ROMDECRST resets the random logic of the CD-ROM decoder, clears the RAM in the CD-ROM
decoder, and masks reset of the CD-ROM decoder.
Bit: 7
LOGI
CRST
Initial value: 0
R/W: R/W
654
RAM INHBUS
RST CAN
—
000
R/W R/W R/W
3
—
0
R/W
2
—
0
R/W
1
—
0
R/W
0
—
0
R/W
Bit Bit Name
Initial
Value R/W Description
7
LOGICRST 0
R/W CD-ROM Decoder Random Logic Reset Signal
A reset signal is output while this bit is set to 1.
6
RAMRST
0
R/W CD-ROM Decoder RAM Clearing Signal
After setting this bit to 1, refer to the RAMCLRST bit in
the RSTSTAT register to confirm that RAM clearing is
complete.
5
INHBUSCAN 0
R/W If this bit is set while the bus-canceling signal is
asserted, the reset signal for the CD-ROM decoder is
masked.
4 to 0 
All 0 R/W Reserved
These bits are always read as 0.The write value should
always be 0.
Note: Before setting LOGICRST to 1, make sure that both the RAMRST and INHBUSCAN bits
are clear and then make the setting by writing B'10000000 to this register.
Rev. 2.00 Sep. 07, 2007 Page 984 of 1312
REJ09B0320-0200