SH7261 Datasheet, PDF (67/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
Addressing Mode Instruction Format Effective Address Calculation
Equation
Register indirect @(disp:4,Rn)
with displacement
The effective address is the sum of Rn and
a 4-bit displacement (disp). The value of disp is
zero-extended, and remains unchanged for
a byte operation, is doubled for a word
operation, and is quadrupled for a longword
operation.
Rn
Byte:
Rn + disp
Word:
Rn + disp × 2
Longword:
Rn + disp × 4
disp
(zero-extended)
+
×
Rn + disp × 1/2/4
Register indirect @(disp:12,Rn)
with displacement
Indexed register
indirect
@(R0,Rn)
1/2/4
The effective address is the sum of Rn and
a 12-bit displacement (disp).
The value of disp is zero-extended.
Rn
+
disp
(zero-extended)
Rn + disp
Byte:
Rn + disp
Word:
Rn + disp
Longword:
Rn + disp
The effective address is the sum of Rn and R0. Rn + R0
Rn
+
Rn + R0
GBR indirect with @(disp:8,GBR)
displacement
R0
The effective address is the sum of GBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and remains unchanged
for a byte operation, is doubled for a word
operation, and is quadrupled for a longword
operation.
GBR
Byte:
GBR + disp
Word:
GBR + disp × 2
Longword: GBR
+ disp × 4
disp
+
(zero-extended)
×
GBR
+ disp × 1/2/4
1/2/4
Rev. 2.00 Sep. 07, 2007 Page 35 of 1312
REJ09B0320-0200