SH7261 Datasheet, PDF (834/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
18.4.5 Receive Operation
Like transmission, reception can be controlled either by DMA or interrupt.
Figures 18.22 and 18.23 show the flow of operation.
When disabling the SSI module, the SSI clock* must be kept supplied until the IIRQ bit is in idle
state.
Note: * Input clock from the SSISCK pin when SCKD = 0.
Input clock from the AUDIO_CLK pin, or AUDIO_X1 and AUDIO_X2 pins when
SCKD = 1.
Rev. 2.00 Sep. 07, 2007 Page 802 of 1312
REJ09B0320-0200