SH7261 Datasheet, PDF (978/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
Input data come from the peripheral bus and output data go out via the peripheral bus along a
single line each, but the bus bridge logic sets up branches for the register access port and stream
data port.
The stream data from the CD-DSP are transferred via the SSI to the stream data input control
block. They are then subjected to descrambling, ECC correction, and EDC checking as they pass
through the CD-ROM decoder. After these processes, data from one sector are obtained. The data
are subsequently transferred to the stream-data buffer via the stream-data output control block.
Data can be transferred by either the DMAC or the CPU.
Figure 21.3 is a block diagram of the bus-bridge logic.
Since the input stream is transferred over the SSI, transfer is relatively slow. On the other hand,
data from the output stream can be transferred at high speeds because they are already in the core
of the CD-ROM decoder. Since the data for output are buffered in SDRAM or other memory, they
must be transferred at high speeds in order to reduce the busy rate of the SDRAM. For this reason,
the data for the output stream are read out before the CD-ROM decoder receives an output stream
data read request from the peripheral bus. This allows the accumulation of streaming data in the
registers of the bus bridge, so that the data are ready for immediate output to the peripheral bus
upon a request from the peripheral bus. Accordingly, the reception of a request to read from
registers other than the stream-data registers after the stream data has already been read out and
stored in the register of the bus bridge is possible. To cope with this, the CD-ROM decoder is
provided with separate intermediary registers for the output stream-data register and the other
registers.
Input data from
the peripheral bus
Data for output to
the peripheral bus
Buffer control signal for
the output stream-data section
Input
stream data
Register data
(write)
Register data
(read)
Output
stream data
Output stream-data
control signal
Figure 21.3 Schematic Diagram of the Bus Bridge
Rev. 2.00 Sep. 07, 2007 Page 946 of 1312
REJ09B0320-0200