SH7261 Datasheet, PDF (397/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Cycle-stealing transfer mode
CKIO
DMA (S)
DMA (D)
DACT (SACT = 0, DACT = 0)
DACT (SACT = 1, DACT = 0)
DACT (SACT = 0, DACT = 1)
DACT (SACT = 1, DACT = 1)
DACK
Single operand transfer (read 0 wait)
RD1
RD2
WR1
WR2
High
Pipeline transfer mode
CKIO
DMA (S)
DMA (D)
DACT (SACT = 0, DACT = 0)
Single operand transfer (read 0 wait)
RD1 RD2 RD3 RD3
WR1 WR2 WR3 WR3
High
DACT (SACT = 1, DACT = 0)
DACT (SACT = 0, DACT = 1)
DAC T (SACT = 1, DACT = 1)
DACK
[Legend]
DMA (S): Internal cycles of source-side access by the DMAC
DMA (D): Internal cycles of destination-side access by the DMAC
Figure 11.11 Timing of DMA Acknowledge and DNA Active Signal Output
Rev. 2.00 Sep. 07, 2007 Page 365 of 1312
REJ09B0320-0200