SH7261 Datasheet, PDF (329/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus Monitor
Bit
Bit Name
12 to 10 
Initial
Value
All 0
9, 8
OMST[1:0] 00
7, 6

All 0
5
SHER
0
4 to 2 
All 0
1, 0
SHMST
00
[1:0]
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Bus Master
These bits indicate the bus master that accessed other
buses when the first bus error occurred.
00: CPU
01: DMAC (destination side)
10: Setting prohibited
11: DMAC (source side)
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Illegal Address Access
This bit indicates that an illegal address access was
made on peripheral bus (2) when the first bus error
occurred.
0: Illegal address access not made
1: Illegal address access made
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Bus Master
These bits indicate the bus master that accessed
peripheral bus (2) when the first bus error occurred.
00: CPU
01: DMAC (destination side)
10: Setting prohibited
11: DMAC (source side)
Rev. 2.00 Sep. 07, 2007 Page 297 of 1312
REJ09B0320-0200