SH7261 Datasheet, PDF (280/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
(b) Page Access Operation
The initial data read/write operation is the same as a normal read/write operation. That is, when
the WAIT signal is low two cycles before the end of the wait cycles (Tend), external wait cycles
are inserted. After the WAIT signal has gone high, the wait cycles end (Tend) two cycles later.
In the second and subsequent read accesses, the page wait cycle is extended if the WAIT signal is
low two cycles before the end of the page access wait cycle (Tend), and the page wait cycles end
two cycles after the WAIT signal has gone high.
Figure 9.6 shows an example of external wait timing for page read access using longword (32-bit)
access to a 16-bit channel.
CKIO
A27 to A0
Ts
(Tend) _→ Tend
(Tend) _→ Tend
Cycle wait
A0
External
wait
Page cycle External
wait
wait
A1
WAIT
CSn
Don't care
RD
WR
D31 to D0
Don't care
Don't care
Figure 9.6 External Wait Timing Example (Page Read Access to 16-Bit Channel)
Rev. 2.00 Sep. 07, 2007 Page 248 of 1312
REJ09B0320-0200