SH7261 Datasheet, PDF (311/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
CKIO
SDRAM command
Single write
ACT DSL WR PRA DSL
Data bus
d
DRCD
(ACT-WR)
DWR
DPCG
(WR-PRA) (PRA-next)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
WR: Write command
DSL: Deselect command
PRA: Precharge-all command
Note: If the interval set in DRAS is longer than the period from when the WR
command is issued until the DRAS interval elapses, the DWR setting
is used.
Figure 9.40 Single Write Timing Example 2
Single write
CKIO
SDRAM command
ACT DSL WR DSL PRA DSL
Data bus
d
DRCD
(ACT-WR)
DWR
(WR-PRA)
DPCG
(PRA-next)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
WR: Write command
DSL: Deselect command
PRA: Precharge-all command
Figure 9.41 Single Write Timing Example 3
Rev. 2.00 Sep. 07, 2007 Page 279 of 1312
REJ09B0320-0200