SH7261 Datasheet, PDF (30/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

27.2.6 System Control Register 1 (SYSCR1) ................................................................ 1136
27.2.7 System Control Register 2 (SYSCR2) ................................................................ 1137
27.2.8 RAM Retaining Area Specifying Register (RAMKP)........................................ 1138
27.2.9 Deep Standby Oscillation Settling Clock Select Register (DSCNT) .................. 1139
27.2.10 Deep Standby Cancel Source Flag Register (DSFR).......................................... 1140
27.3 Operation ......................................................................................................................... 1142
27.3.1 Sleep Mode ......................................................................................................... 1142
27.3.2 Software Standby Mode...................................................................................... 1143
27.3.3 Software Standby Mode Application Example................................................... 1145
27.3.4 Deep Standby Mode ........................................................................................... 1146
27.3.5 Module Standby Function................................................................................... 1151
27.4 Usage Note....................................................................................................................... 1151
27.4.1 Note on Setting Registers ................................................................................... 1151
27.4.2 Note on Canceling Standby Mode when an External Clock is being Input ........ 1151
Section 28 User Debugging Interface (H-UDI)............................................... 1153
28.1 Features............................................................................................................................ 1153
28.2 Input/Output Pins............................................................................................................. 1154
28.3 Register Descriptions....................................................................................................... 1155
28.3.1 Bypass Register (SDBPR) .................................................................................. 1155
28.3.2 Instruction Register (SDIR) ................................................................................ 1156
28.4 Operation ......................................................................................................................... 1157
28.4.1 TAP Controller ................................................................................................... 1157
28.4.2 Reset Types......................................................................................................... 1158
28.4.3 UDTDO Output Timing...................................................................................... 1158
28.4.4 H-UDI Reset ....................................................................................................... 1159
28.4.5 H-UDI Interrupt .................................................................................................. 1159
28.5 Usage Notes ..................................................................................................................... 1160
Section 29 Advanced User Debugger II (AUD-II).......................................... 1161
29.1 Features............................................................................................................................ 1161
29.2 Input/Output Pins............................................................................................................. 1161
29.3 RAM Monitor Mode........................................................................................................ 1163
29.3.1 Communication Protocol .................................................................................... 1163
29.3.2 Operation ............................................................................................................ 1164
29.3.3 Usage Notes (RAM Monitor Mode) ................................................................... 1166
Section 30 List of Registers............................................................................. 1167
30.1 Register Addresses (Address Order)................................................................................ 1168
30.2 Register Bits..................................................................................................................... 1189
Rev. 2.00 Sep. 07, 2007 Page xxx of xxxii