SH7261 Datasheet, PDF (1335/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions and Additions in this Edition
Item
Page Revision (See Manual for Details)
19.6.1 Configuration of RCAN-ET 860 Modified
(4) CAN sleep mode
• Don't set MCR5 (Sleep Mode) without entering Halt
Mode.
• After setting MCR1, make sure that GSR4 is set and
the RCAN-ET has entered Halt Mode before clearing
MCR1.
20.8 Usage Notes
941, Added
942
22.7.7 Usage Note when Shifting 1036 Added
to Single Mode during A/D
Conversion
27.2.9 Deep Standby Oscillation
Settling Clock Select Register
(DSCNT)
1139 Notes added
Bit Bit Name
2 to 0 CKS[2:0]
Description
Clock Select
:
Setting
value
Clock
select
000:
001:
010:
011:
100:
1 × Pφ*¹
1/64 × Pφ*¹
1/128 × Pφ*¹
1/256 × Pφ*²
1/512 × Pφ*²
Notes: 1. Do not use this setting.
2. Set the clock so that it is equal to or longer than the
oscillation settling time 2 on return from standby
(tOSC3).
27.2.10 Deep Standby Cancel
Source Flag Register (DSFR)
1140, Added
1141 _{Note: * Only 0 can be written after reading 1 to clear the}
flag.
Even when IRQ is input after a manual reset
has been accepted as a source canceling deep
standby, the IRQ flag is not set.
27.4.1 Note on Setting Registers 1151 Title added
27.4.2 Note on Canceling Standby 1151 Added
Mode when an External Clock is
being Input
Rev. 2.00 Sep. 07, 2007 Page 1303 of 1312
REJ09B0320-0200