SH7261 Datasheet, PDF (186/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
Number of States
Item
Peripheral
NMI
User Break H-UDI
IRQ, PINT Module Remarks
Interrupt
response
time
No
register
banking
Min. 5 Icyc +
2 Bcyc +
1 Pcyc +
m1 + m2
6 Icyc +
m1 + m2
5 Icyc +
1 Pcyc +
m1 + m2
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
120-MHz operation*¹*²:
0.067 to 0.142 µs
Max.
6 Icyc +
7 Icyc +
6 Icyc +
6 Icyc +
6 Icyc +
120-MHz operation*¹*²:
2 Bcyc + 2 (m1 + m2) 1 Pcyc + 3 Bcyc + 1 Bcyc + 0.100 to 0.175 µs
1 Pcyc + + m3
2 (m1 + m2) 1 Pcyc + 1 Pcyc +
2 (m1 + m2)
+ m3
2 (m1 + m2) 2 (m1 + m2)
+ m3
+ m3
+ m3
Register Min. 

5 Icyc +
5 Icyc +
5 Icyc +
120-MHz operation*¹*²:
banking
1 Pcyc + 3 Bcyc + 1 Bcyc + 0.092 to 0.142 µs
without
m1 + m2 1 Pcyc + 1 Pcyc +
register
m1 + m2 m1 + m2
bank
Max. 

14 Icyc + 14 Icyc + 14 Icyc + 120-MHz operation*¹*²:
overflow
1 Pcyc + 3 Bcyc + 1 Bcyc + 0.167 to 0.217 µs
m1 + m2 1 Pcyc + 1 Pcyc +
m1 + m2 m1 + m2
Register Min. 

5 Icyc +
5 Icyc +
5 Icyc +
120-MHz operation*¹*²:
banking
1 Pcyc + 3 Bcyc + 1 Bcyc + 0.092 to 0.142 µs
with
m1 + m2 1 Pcyc + 1 Pcyc +
register
m1 + m2 m1 + m2
bank
Max. 

5 Icyc +
5 Icyc +
5 Icyc +
120-MHz operation*¹*²:
overflow
1 Pcyc + 3 Bcyc + 1 Bcyc + 0.245 to 0.300 µs
m1 + m2 + 1 Pcyc + 1 Pcyc +
19 (m4) m1 + m2 + m1 + m2 +
19 (m4)
19 (m4)
Notes: m1 to m4 are the number of states needed for the following memory accesses.
m1: Vector address read (longword read)
m2: SR save (longword write)
m3: PC save (longword write)
m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the
stack.
1. In the case of m1 = m2 = m3 = m4 = 1 Icyc.
2. In the case of Iφ:Bφ:Pφ = 120:60:30 [MHz].
Rev. 2.00 Sep. 07, 2007 Page 154 of 1312
REJ09B0320-0200