SH7261 Datasheet, PDF (630/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(28) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and
Operation is Restarted in Complementary PWM Mode
Figure 12.152 shows an explanatory diagram of the case where an error occurs in reset-
synchronized PWM mode and operation is restarted in complementary PWM mode after re-
setting.
1
2
3
4
5
6
Power-on TOCR TMDR TOER PFC TSTR
MTU2
reset
(RPWM) (1) (MTU2) (1)
module output
7
8
9
10
Match Error PFC TSTR
occurs (PORT) (0)
11
TOER
(0)
12
13
14
15
16
TOCR TMDR TOER PFC TSTR
(CPWM) (1) (MTU2) (1)
TIOC3A
TIOC3B
TIOC3D
Port output
PB16
PB17
High-Z
High-Z
PB19
High-Z
Figure 12.152 Error Occurrence in Reset-Synchronized PWM Mode,
Recovery in Complementary PWM Mode
1 to 10 are the same as in figure 12.150.
11. Disable channel 3 and 4 output with TOER.
12. Select the complementary PWM output level and cyclic output enabling/disabling with
TOCR.
13. Set complementary PWM. (The MTU2 cyclic output pin goes low.)
14. Enable channel 3 and 4 output with TOER.
15. Set MTU2 output with the PFC.
16. Operation is restarted by TSTR.
Rev. 2.00 Sep. 07, 2007 Page 598 of 1312
REJ09B0320-0200