SH7261 Datasheet, PDF (105/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 3 Floating-Point Unit (FPU)
Initial
Bit
Bit Name Value R/W
17 to 12 Cause
All 0 R/W
11 to 7 Enable All 0 R/W
6 to 2 Flag
All 0 R/W
1
RM1
0
R/W
0
RM0
1
R/W
Description
FPU Exception Cause Field
FPU Exception Enable Field
FPU Exception Flag Field
When an FPU exception occurs, the bits corresponding
to the FPU exception cause field and FPU exception
flag field are set to 1. Each time an FPU operation
instruction is executed, the FPU exception cause field
is cleared to 0. The FPU exception flag field remains
set to 1 until it is cleared to 0 by software.
For bit allocations of each field, see table 3.3.
Rounding Mode
These bits select the rounding mode.
00: Round to Nearest
01: Round to Zero
10: Reserved
11: Reserved
Table 3.3 Bit Allocation for FPU Exception Handling
Field Name
FPU
Invalid
Division Overflow Underflow Inexact
Error (E) Operation (V) by Zero (Z) (O)
(U)
(I)
Cause
FPU exception
cause field
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Enable
FPU exception
enable field
None
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Flag
FPU exception flag None
Bit 6
field
Bit 5
Bit 4
Bit 3
Bit 2
Note: No FPU error occurs in the SH2A-FPU.
3.3.3 Floating-Point Communication Register (FPUL)
Information is transferred between the FPU and CPU via FPUL. FPUL is a 32-bit system register
that is accessed from the CPU side by means of LDS and STS instructions. For example, to
convert the integer stored in general register R1 to a single-precision floating-point number, the
processing flow is as follows:
R1 → (LDS instruction) → FPUL → (single-precision FLOAT instruction) → FR1
Rev. 2.00 Sep. 07, 2007 Page 73 of 1312
REJ09B0320-0200