SH7261 Datasheet, PDF (719/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
5
TDFE
1
R/(W)* Transmit FIFO Data Empty
Indicates that data has been transferred from the
transmit FIFO data register (SCFTDR) to the transmit
shift register (SCTSR), the quantity of data in
SCFTDR has become less than the transmission
trigger number specified by the TTRG1 and TTRG0
bits in the FIFO control register (SCFCR), and writing
of transmit data to SCFTDR is enabled.
0: The quantity of transmit data written to SCFTDR is
greater than the specified transmission trigger
number
[Clearing conditions]
• TDFE is cleared to 0 when data exceeding the
specified transmission trigger number is written to
SCFTDR after 1 is read from TDFE and then 0 is
written
• TDFE is cleared to 0 when the DMAC is activated
by the transmit FIFO data empty interrupt (TXI)
and writes data exceeding the specified
transmission trigger number to SCFTDR
1: The quantity of transmit data in SCFTDR is less
than or equal to the specified transmission trigger
number*¹
[Setting conditions]
• TDFE is set to 1 by a power-on reset
• TDFE is set to 1 when the quantity of transmit
data in SCFTDR becomes less than or equal to
the specified transmission trigger number as a
result of transmission
Note: 1. Since SCFTDR is a 16-byte FIFO register,
the maximum quantity of data that can be
written when TDFE is 1 is "16 minus the
specified transmission trigger number". If an
attempt is made to write additional data, the
data is ignored. The quantity of data in
SCFTDR is indicated by the upper 8 bits of
SCFDR.
Rev. 2.00 Sep. 07, 2007 Page 687 of 1312
REJ09B0320-0200