SH7261 Datasheet, PDF (835/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

(1) Reception Using DMA Controller
Section 18 Serial Sound Interface (SSI)
Start
Release from reset,
define SSICR configuration bits.
Setup DMA controller
to transfer data
from SSI module to memory.
Enable SSI module,
enable DMA,
enable error interrupts.
Wait for interrupt from DMAC or SSI
Define TRMD, EN, SCKD, SWSD,
MUEN, DEL, PDTA, SDTA, SPDP,
SWSP, SCKP, SWL, DWL, CHNL.
EN = 1,
DMEN = 1,
UIEN = 1, OIEN = 1
Yes
SSI error interrupt?
No
No
DMAC:
End of Rx data?
Yes
Yes
More data to be send?
No
Disable SSI module,
disable DMA,
disable error interrupts,
enable Idle interrupt.
EN = 0,
DMEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Wait for idle interrupt
from SSI module.
End*
Note: * If the SSI encounters an error interrupt underflow/overflow,
go back to the start in the flowchart again.
Figure 18.22 Reception Using DMA Controller
Rev. 2.00 Sep. 07, 2007 Page 803 of 1312
REJ09B0320-0200